The error pin counter in the system Instrument Cluster (IC) does not increment error pin events or decouple bits that are not reset by the system IC. The failsafe logic test pulls the error pin in order to test the error pin event counter within the system chip. To prevent an electrical shutdown, which would disturb communication, during the provoked error pin event, the electrical decouple bit is set. It is also tested that the decouple bit gets reset.