The Serial Peripheral Interface (SPI) failure detection unit of each Application-specific integrated circuit (ASIC) (system ASIC / Valve ASIC / RFP ASIC) is tested for correct detection and response of parity, address, and clock failures on the SPI protocol. 

The initial test of the SPI failure detection functionality in any ASIC inside the electronic control unit (ECU) failed (SPI address Read / Write test, SPI parity test, and SPI clock test). This could indicate that wrong data is being sent to the ASIC or there is a defect in the SPI transceiver or the SPI lines.